The present invention relates generally to n-channel FET one-device memory cells of minimum dimensions, and the preparation of integrated circuits containing arrays of these cells. More particularly, the present invention relates to n-channel FET one-device memory cells which employ two separately deposited and separately delineated polycrystalline silicon (i.e., polysilicon) layers wherein one of the layers provides the gate of the FET and the other layer provides the upper electrode of the charge storage capacitor, and the preparation of integrated circuit arrays of these cells. The lower electrode of the charge storage capacitor is a semiconductive region of n-conductive type upon which charge representing information can be stored. The present invention provides FET memory cells which have a self-registering electrical connection between the metallic interconnection word line and the polysilicon gate of the FET. Moreover, the present invention is directed to what is commonly referred to as "metal word line/diffused bit line" memory cell arrays as distinguished from "metal bit line/polysilicon word line" memory cell arrays. The present invention requires only five basic lithographic (pattern delineating) masking steps to achieve the desired integrated circuit comprising an array of one-device memory cells and the associated addressing, decoding, and sensing circuits which are positioned peripherally to the array.
The FET one-transistor-per-memory-cell (one-device memory cell) represents the most densely packed, highest performance, integrated circuit, random access memory device available on the market today. Such semiconductor memories use the so-called "one-device cell" which consists of a single field-effect transistor (FET) switch and a conductor-insulator-semiconductor information storage capacitor. The FET is used to switch electronic charges (electrons) representing information into and out of the capacitor. Typically the charge storage capacitor is operated in two states, charged and uncharged, representing a binary "1" and "0". The upper electrode of the storage capacitor can be referred to as the plate of the one-device cell.
Various methods are known in the art for preparing integrated circuit arrays of FET one-device memory cells having metal word lines and diffused bit lines. One of the first of this type of one-device memory cell known was a metal gate/metal plate cell with a doped storage region described by Dennard in U.S. Pat. No. 3,387,286. Arrays of this type of device require four basic masking steps, but the cells are relatively very large in area because the metal gate word line cannot pass over the metal storage capacitor plate.
Smith in U.S. Pat. No. 3,811,076 and Garnache et al in U.S. Pat. No. 3,841,926 describe four mask methods for fabricating an integrated circuit array of one-device memory cells which employ a metal gate, and a polysilicon storage electrode which also serves as a field shield for isolation between cells. The fabrication processes suggested by Smith and by Garnache et al make it possible to obtain high density memory cells with doped storage regions. However, the fabrication methods and subsequent cells disclosed by Smith and by Garnache et al require that the field shield overlap the bit line thereby resulting in a relatively high capacitive coupling between the bit line and the field shield (storage plate) which for best circuit performance should be as low as possible.
In addition, Dennard, Rideout, and Walker in U.S. Pat. No. 3,899,363 illustrate the fabrication of one-device memory cells utilizing recessed oxide isolation regions for electrically insulating one cell from another in a densely packed integrated circuit array. The fabrication method suggested by Dennard et al employs four basic masking steps and utilizes one layer of polysilicon. However, the devices obtained by such a process are relatively large as compared to the devices achieved by the process of the present invention because they require a conventional etched contact hole in order to electrically connect the metallic word line to the polysilicon gate. The contact hole is etched through an insulating oxide layer that exists over the polysilicon gate. Furthermore, the storage region is provided by an inversion layer as opposed to a doped storage electrode as obtained by the present invention.
Inversion storage is not entirely desirable because it requires an additional power supply for the upper capacitor electrode to maintain the inversion layer. Generally, the voltage supplied to the upper capacitor electrode is larger in absolute magnitude than the voltage supplied to the word line, and different in polarity from that supplied to the semiconductive substrate. Furthermore, in an inversion storage device, a pin hole in the storage capacitor insulator can cause a deleterious high leakage current due to the required difference in supply voltages between the upper storage capacitor electrode and the semiconductive substrate.
With a doped storage device there is no need to provide a power supply to maintain an inversion layer because the doped region provides the necessary electrons. Consequently, the upper storage electrode can be maintained at the same voltage as the substrate. Not only does this eliminate one power supply, but, in addition, pinholes in the capacitor insulator do not cause a deleterious high leakage current because the upper storage capacitor electrode and the semiconductive substrate are maintained at the same voltage.
Exemplary of still another fabrication method for an integrated circuit array of one-device memory cells is that described by Dennard et al in U.S. Pat. No. 3,834,959 which involves a metal gate such as an aluminum gate and a polysilicon storage plate. This technique results in a thick recessed silicon-dioxide isolation between adjacent cells and requires five basic masking steps. The storage method, however, is inversion storage and, accordingly, is not entirely desirable for reasons discussed hereinabove.
A fabrication process suggested by Kalter and Miller in IBM Technical Disclosure Bulletin, Volume 14, No. 10, March 1972, provides polysilicon gate FETs in which a metal word line is "self-registered" with respect to a polysilicon gate. In the fabrication process disclosed by Kalter et al, oxidation over the polysilicon gate is prevented by an oxidation barrier gate masking layer. When the oxidation barrier layer is removed, the entire gate area is revealed for contacting. A metal word line such as aluminum that crosses the polysilicon gate will provide an electrical connection to that gate. Because the entire gate area is revealed, the metal word line and the polysilicon gate advantageously do not need to be precisely registered with respect to each other in order to make electrical connection. Much more precise registration is required, however, when the metal line must contact the polysilicon gate via a conventional contact hole etched through an oxide layer that exists over the gate. However, the process suggested by Kalter et al requires an inversion storage under the capacitor plate and, accordingly, is therefore not completely satisfactory.
Also, the inventor of the present application suggested, for instance, in IBM Technical Disclosure Bulletin, Vol. 17, No. 9, February 1975, a fabrication process involving five basic masking steps to provide integrated circuits of relatively small one-device memory cells having thick oxide isolation between cells and a self-registering connection between a conductive word line and a polysilicon gate. However, this fabrication process, which employs five basic lithographic masking steps, utilized a single layer of polysilicon which results in inversion storage beneath the capacitor and is therefore not completely satisfactory.
In the fabrication of FET one-device memory cells it is desirable to use polysilicon for both the gate of the FET switch and the plate of the storage capacitor. As is well known in the art, polysilicon is an attractive FET gate material because of its ability to withstand high processing temperatures without degradation, which allows fabrication of source and drain self-aligned with respect to the gate. Furthermore, polysilicon offers potentially higher gate oxide reliability than other gate materials. Electrical insulation layers can be deposited or grown on polysilicon capacitor plates, which allows another interconnection material to cross over them, thereby facilitating the internal on-chip wiring of integrated circuits. In addition, polysilicon can serve as an interconnection material.
Accordingly, the prior art suggestions including the five masking step processes do not provide integrated circuits of one-device memory cells having all of the following desirable aspects:
(1) doped polysilicon gate; PA1 (2) doped polysilicon upper storage capacitor electrode (plate); PA1 (3) doped lower storage capacitor electrode; PA1 (4) thick oxide isolation between memory cells of the array; PA1 (5) self-registering electrical connection between the doped polysilicon gate and the metallic-type high-conductivity word line; PA1 (6) doped bit line. PA1 (1) doped polysilicon gate; PA1 (2) doped polysilicon upper capacitor electrode (plate); PA1 (3) doped lower capacitor electrode; PA1 (4) thick field oxide isolation between memory cells of the array; PA1 (5) self-registering electrical connection between the doped polysilicon gate and the metallic-type high-conductivity word line; PA1 (6) doped bit line. PA1 (A) providing a semiconductive substrate of p-conductive type containing active impurities of p-type; PA1 (B) providing and delineating predetermined oxide regions above or recessed into the substrate to provide isolating field oxide regions between memory cells of the array; PA1 (C) providing an FET gate insulator; PA1 (D) depositing and doping a layer of polycrystalline silicon above the gate insulator; PA1 (E) then delineating the predetermined polycrystalline silicon gate regions of the FETs with an oxidation barrier layer; PA1 (F) thermally diffusing or ion implanting active impurities of n-type into predetermined regions of the semiconductive substrate to provide doped bit lines (FET drains), connection regions (FET sources), and lower silicon electrodes of the storage capacitors above which electrodes are to be subsequently delineated polycrystalline silicon upper electrodes of the storage capacitors; PA1 (G) providing a capacitor insulator; PA1 (H) then depositing and doping a second and subsequent layer of polycrystalline silicon above the capacitor insulator; PA1 (I) then delineating the second and subsequent polycrystalline silicon layer to provide predetermined polycrystalline silicon upper electrode regions above the corresponding n-type doped silicon lower electrodes of the storage capacitors; PA1 (J) thermally growing a silicon dioxide insulating layer over regions of the structure but not over the polycrystalline silicon FET gates which are still protected by an oxidation barrier layer; PA1 (K) removing the oxidation barrier layer from over the FET gates by use of an etchant; PA1 (L) delineating contact holes to polycrystalline silicon upper capacitor electrodes; and to n-type source and drain regions in circuits peripheral to the array of memory cells; PA1 (M) next depositing and delineating a metallic-type high-conductivity electrical interconnection pattern that makes electrical connection to the polycrystalline silicon FET gates in the array of memory cells; to polycrystalline silicon upper capacitor electrodes; and to FET sources, gates, and drains in circuits peripheral to the array of memory cells. PA1 (1) delineating field area and device area pattern; PA1 (2) delineating FET gate pattern; PA1 (3) delineating upper storage capacitor electrode pattern; PA1 (4) delineating contact hole pattern to provide vias to upper capacitor electrode and to n-type source and drain regions; PA1 (5) delineating high-conductivity interconnective line pattern. PA1 (A) semiconductive substrate of p-conductive type containing active impurities of p-type; PA1 (B) doped polycrystalline silicon FET gate; PA1 (C) doped polycrystalline silicon upper storage capacitor electrode; PA1 (D) doped n-conductive type lower storage capacitor electrode; PA1 (E) doped n-conductive type bit line; PA1 (F) metallic-type high-conductivity word line; PA1 (G) self-registering electrical connection between the doped polycrystalline silicon gate and the word line; PA1 (H) oxide isolation between said memory cell and other memory cells on the same semiconductive substrate; and PA1 (I) silicon dioxide insulation over regions of the structure but not over the FET gates.
The lithographic masking steps involved in preparing integrated circuits are among the most critical. The lithographic masking steps require high precision in registration and extreme care in execution. Each additional lithographic masking step in a process introduces possible surface damage due to mask defects, and increases mask-to-mask registration problems that decrease the processing yield and, accordingly, significantly increase the fabrication cost. Although other factors affect the yield and cost such as, for example, the number of high temperature heat treatments, a basic objective in all FET integrated circuit fabrication is to minimize the number of basic lithographic masking steps required to produce a particular integrated circuit array of desired device structures.
Accordingly, an object of the present invention is to provide FET one-device cell memories having all of the above-discussed desirable aspects. Another object of the present invention is to provide a fabrication process for producing integrated circuits of FET one-device memory cells which requires a minimum number of masking steps. In particular, it is an object of the present invention to provide a fabrication process which requires only five basic lithographic masking steps in order to prepare integrated circuits containing arrays of one-device memory cells having all of the following desirable characteristics:
The present fabrication process which employs only five lithographic masking steps is relatively easy to perform and does not to any great extent increase the overall processing time and expense over prior art processes employing five masking steps. Such prior art processes do not produce the desirable integrated circuit memory cell arrays achieved by the present invention.